1. Field of the Invention
Generally, the subject matter disclosed herein relates to the formation of integrated circuits, and, more particularly, to the formation of transistors having strained channel regions by using stress sources, stressed overlayers and the like to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Generally, a plurality of process technologies are currently practiced in the field of semiconductor production, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length is a dominant design criterion for accomplishing an increase in the operating speed and packing density of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is providing low sheet and contact resistivity in drain and source regions and any contacts connected thereto and maintaining channel controllability. For example, reducing the channel length may necessitate an increase of the capacitive coupling between the gate electrode and the channel region, which may call for reduced thickness of the gate insulation layer. Presently, the thickness of silicon dioxide based gate insulation layers is in the range of 1-2 nm, wherein a further reduction may be less desirable in view of leakage currents which typically exponentially increase when reducing the gate dielectric thickness.
The continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques concerning the above-identified problems. It has been proposed to improve transistor performance by enhancing the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the above-mentioned problems such as gate dielectric scaling. One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, for standard silicon substrates, creating tensile strain in the channel region increases the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity and thus drive current and operating speed. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
According to one promising approach, stress may be created by, for instance, layers located close to the transistor, spacer elements and the like to induce a desired strain within the channel region. However, the process of creating the strain in the channel region by applying a specified external stress may suffer from an inefficient translation of the external stress into strain in the channel region. Hence, although providing significant advantages, the efficiency of the stress transfer mechanism may depend on the process and device specifics and may result in a reduced performance gain for well-established standard transistor designs, since the overlaying layer may be significantly offset from the channel region, thereby reducing the strain finally created in the channel region. Therefore, recessed transistor architectures have been proposed for enhancing the lateral stress transfer.
With reference to FIGS. 1a-1g, conventional strategies for forming recessed transistor architectures will now be described in more detail in order to explain principal advantages of this device configuration and also describe problems, especially involved with SOI (silicon-on-insulator) architectures.
FIG. 1a schematically illustrates a top view of a semiconductor device 100 comprising a transistor element 150. The transistor element 150 typically comprises drain and source regions 151 and a gate electrode 152, which may have formed on the sidewalls thereof respective sidewall spacers 153. Furthermore, respective contacts 157 may extend substantially perpendicular to the drawing plane of FIG. 1a so as to establish electrical connections of the drain and source regions 151 to a respective higher wiring level (not shown). Furthermore, a respective dielectric material for passivating the material 150 may not be shown in FIG. 1a so as to not unduly obscure the respective structure of the transistor element 150.
FIG. 1b schematically illustrates a cross-sectional view of the semiconductor device 100 taken along the line Ib-Ib of FIG. 1a. First, a substantially planar configuration is shown in FIG. 1b in order to demonstrate the advantages of a recessed transistor configuration, as will be explained in more detail with reference to FIGS. 1c-1d. In FIG. 1b, the semiconductor device 100 comprises a substrate 101, which represents a bulk silicon substrate including, on an upper portion thereof, a semiconductor layer 102. Hence, the transistor 150 may represent a bulk transistor wherein the drain and source regions 151 and a corresponding channel region 155 are electrically connected to the substrate 101. Moreover, in this manufacturing stage, respective metal silicide regions 154 may also be formed on the gate electrode 152 and in the drain and source regions 151, wherein a corresponding lateral offset to the gate electrode 152 may be substantially defined by the spacer structure 153. For convenience, the metal silicide regions 154 are not shown in FIG. 1a. 
Moreover, a strain-inducing dielectric layer 103, for instance a silicon nitride layer, is formed above the transistor 150 so as to induce a desired type of strain in the channel region 155. Typically, the dielectric layer 103 may represent a portion of an interlayer dielectric material provided to encapsulate the transistor 150 prior to forming respective wiring levels or metallization layers (not shown) which provide the required electrical connections of respective circuit elements in the semiconductor device 100. When the transistor 150 represents an N-channel transistor, tensile strain in the channel region 155 may significantly enhance the electron mobility therein, thereby providing enhanced transistor performance. In this case, the dielectric material of the layer 103 may be provided with a high intrinsic tensile stress in order to mechanically transfer stress into the channel region 155.
It should be appreciated that highly efficient strain-inducing mechanisms may be available for P-channel transistors, such as the provision of embedded silicon/germanium material in the respective drain and source regions 151, thereby enabling significant transistor improvements for PMOS transistors, wherein, additionally, appropriately stressed dielectric materials, such as the layer 103, may be provided, however, in this case, with a high compressive stress, in order to even further enhance the overall transistor performance. Silicon nitride is well known to be capable of being provided with high intrinsic stress, wherein well-established deposition techniques on the basis of plasma enhanced chemical vapor deposition (PECVD) result in high intrinsic stress, wherein extremely high compressive values may be obtained, while a respective tensile strain is less pronounced. Consequently, in the following, it may be assumed that the transistor 150 may represent an N-channel transistor whose performance is to be further enhanced in order to reduce the imbalance in performance gain of P-channel transistors and N-channel transistors by strain engineering techniques. For example, the respective mechanical transfer of stress into the channel region 155 may be enhanced by recessing the drain and source regions 151 in order to provide an increased “direct” stress component acting substantially laterally on the channel region 155.
FIG. 1c schematically illustrates the semiconductor device 100 including the transistor 150 with a recessed drain and source architecture. That is, the drain and source regions 151 comprise a surface portion 151R that is located at a significantly lower height level with respect to the channel region 155, when compared with the situation of the substantially planar configuration as shown in FIG. 1b. Therefore, the stressed material of the layer 103 may act in a substantially lateral direction, as previously explained. Additionally, the recessed architecture provides an increased surface area of the metal silicide regions 154 in the drain and source regions 151, since an additional sidewall area 151s of the recessed drain and source regions 151 may be available during the corresponding silicidation process. Consequently, the overall series resistance of the transistor 150 may be reduced compared to the planar configuration as shown in FIG. 1b. 
For this reason, the corresponding manufacturing sequence for forming the transistor element 150 as shown in FIG. 1b may be appropriately modified to introduce additional process steps for forming a corresponding recess in the drain and source regions 151 resulting in the transistor configuration as shown in FIG. 1c. For example, well-established process techniques may be used for forming the transistor 150 as shown in FIG. 1c up to a state where the drain and source regions 151 are to be formed in the semiconductor layer 102. During the corresponding process sequence, the implantation sequence may be appropriately designed to obtain the desired depth of the drain and source regions 151 in order to take into consideration the desired degree of recess to be formed therein. As may be evident from the explanation given above, an increased depth of the surface 151R may result in increased performance gain due to the increased efficiency of the stress transfer and the increased amount of metal silicide in the regions 154. Hence, in the bulk transistor configuration as shown in FIG. 1c, a respective adaptation of conventional process techniques may be used to obtain the desired depth of the recessed drain and source regions 151, which may be formed on the basis of an appropriately designed etch process. During the corresponding etch process, other transistor elements, such as P-channel transistors or any other transistors that do not require the recessed configuration, may be appropriately covered by a corresponding etch mask. Thereafter, further processing may be continued on the basis of well-established techniques, for instance by forming the metal silicide regions 154 and depositing the dielectric layer 103 on the basis of appropriate deposition parameters in order to obtain the desired high degree of intrinsic stress. Thereafter, an interlayer dielectric material 104, such as silicon dioxide, may be deposited on the basis of well-established techniques.
FIG. 1d schematically illustrates the transistor 150 of FIG. 1c shown according to a cross-sectional view as indicated by line Id-Id in FIG. 1a. Thus, the contacts 157, which may be comprised of any appropriate conductive material, such as tungsten, copper, silver or any other materials and alloys, may extend through the interlayer dielectric material 104 and the stressed layer 103 to the metal silicide regions 154. The contacts 157 may be formed on the basis of anisotropic etch techniques, wherein the layer 103 may be efficiently used as an etch stop material for first patterning the material 104. Thereafter, the layer 103 may be opened and the resulting openings may be subsequently filled by the desired conductive material. Hence, significant advantages may be obtained by the recessed configuration in terms of strain and series resistance, wherein a respective performance gain is substantially determined by the depth of the respective drain and source regions 151. The depth is substantially limited by the location of the PN junctions of the drain and source regions 151 since the metal silicide regions 154 must not extend beyond the respective PN junctions. Thus, in the bulk configuration, the respective transistor design may be modified to obtain the desired depth of the drain and source regions 151 without shorting the respective PN junctions by appropriately designing the respective dopant profile.
With reference to FIGS. 1e-1g, further advantages of a recessed transistor configuration will be illustrated. In FIG. 1e, the semiconductor device 100 comprises neighboring transistor elements 150A, 150B according to a planar configuration, wherein each of the transistors 150A, 150B may substantially correspond to the transistor as shown in FIG. 1d. In this configuration, the contact 157 may be positioned between the two transistors 150A, 150B, wherein the metal silicide region 154 may provide sufficient drive current capability in order to avoid undue increase of series resistance, since significant current crowding in the metal silicide region 154 may be avoided, although the conductivity of the contact 157 may be significantly higher compared to the conductivity of metal silicide in the region 154, which in turn is significantly higher compared to the conductivity of the drain and source regions 151.
FIG. 1f schematically illustrates the semiconductor device 100 in advanced applications, wherein the corresponding spacing between the neighboring transistors 150A, 150B may be significantly reduced, thereby resulting in a significantly reduced ratio of the lateral extension of the metal silicide region 154 and the contact 157. In the example shown in FIG. 1f, this ratio may even become approximately 1, thereby resulting in a significant current crowding within the metal silicide material, which may unduly reduce the overall performance of the semiconductor device 100 due to increased current crowding at portions 157A.
FIG. 1g schematically illustrates a semiconductor device 100 similar to the device of FIG. 1f wherein, however, a recessed drain and source configuration is used, as is previously explained with reference to FIGS. 1c and 1d. As is evident, due to the increased interface between the contact 157 and the metal silicide region 154 at the areas 157A, undue increase of the series resistance may be avoided or at least reduced, thereby also making the recessed drain and source configuration highly advantageous in semiconductor devices requiring reduced spacings between neighboring transistor elements.
In principle, the recessed transistor configuration may also be advantageous in the context of SOI devices, wherein, however, the depth of the recess of the SOI configuration is limited by the initial thickness of the semiconductor layer formed above the buried insulating layer. Thus, techniques have been proposed to etch the recess close to the buried insulating layer yet maintain sufficient silicon as required by the subsequent silicide process. That is, in order to maintain silicide integrity, a residual layer is maintained, the thickness of which is substantially determined by the silicide thickness required in the gate electrode for obtaining the desired low gate resistance. For example, in modern SOI transistors having a recessed drain/source configuration, a minimum thickness of approximately 20 nm may be required in order to provide process uniformity and silicide integrity. Hence, there is still room for improvement in enhancing performance of SOI transistors having a recessed drain/source configuration.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.